1. Field of the Invention
The present invention relates to a fault coverage testing technique, and more particularly, to a method and system for testing a memory of an integrated circuit for faults.
2. Description of the Related Art
Memory cells of memory devices have been tested using many different techniques. Memory devices include, for example, commercial memory chips and VLSI designs having memory. VLSI designs include, for example, application specific integrated circuits (ASIC) which often include a random access memory (RAM).
Memory devices can be tested using internal or external means. External testing is typically performed by manufacturers of commercial memory chips. Although external testing is thorough, it requires the generation of many test vectors to obtain sufficient fault coverage. Test vectors are external stimulants which are supplied to test the memory. The more test vectors required the more inefficient the testing. Functional testing is another external testing technique which has been previously used, but it requires an understanding of the functionality of the circuit. Thus, in general, external testing is very time consuming.
Internal testing has been used to test a memory, but it often does not provide sufficient fault coverage. One major disadvantage of conventional internal testing is that a large amount of additional gates must be added to the integrated circuit. This reduces the available space on the integrated circuit for other circuitry or increases the chip area dedicated to the memory and its associated circuitry. In some commercial memory devices, additional test circuits are added which while being efficient, are not available for use on ASICs.
In sum, prior techniques for testing memory typically require complicated circuitry and large quantities of test vectors. For example, conventionally, when testing a memory, at least four test vectors are supplied to test each bit, two read clocks and two write clocks. Numerous additional test vectors are conventionally thereafter required to test elements of the integrated circuit, such as, address lines, address decoder, data lines, data buffer, etc. which are associated with the memory. Therefore, prior techniques inefficiently use test vectors or additional circuitry to obtain fault coverage. The more test vectors utilized, the more complicated the testing circuitry becomes.